主要意思是不能让poly和OD周围太空，不对称，密度太低，因此通过加endcap（通常是FILLER2 ，FILLER1没有OD ，不行）来满足均匀的密度， 是的std cell 周围的环境一致，
一般来说对block level是 必须做的，因为在chip level来看必须是一致的密度，
welltap这个就是偏置nwell和psub ， 适应7-track等小std cell， 一般为50~60um一个半径
来加，棋盘式加入， 这个不是40nm的独有， 早在180nm的时候就有了，
decap 就是去耦啊，特殊的filler cell， 可以降低动态电压降， 满足一定的电容值，
gate array类型的decap（比如tsmc的GDCAP）还可以起到eco cell的作用，
40nm就是多了个endcap， dfm更加重视些， 不能用FILLER1了
Placing the Well Tap Cells
Well taps are physical-only filler cells that are required by some technology libraries to limit
resistance between power or ground connections to wells of the substrate. Well-tap cells are
placed in a pre-placed status, so future placement commands do not move them.
The placer places the cells in accordance to the specified distances and automatically snaps
them to legal positions (which are the core sites).
Placing the End Cap Cells
These library cells do not have signal connectivity. They connect only to the power and ground rails once power rails are created in the design.
They also ensure that gaps do not occur between the well and implant layers.
This prevents DRC violations by satisfying well tie-off requirements for the core rows.
Each end of the core row, left and right, can have only one end cap cell specified. However, you
can specify a list of different end caps for inserting horizontal end cap lines, which terminate the
top and bottom boundaries of objects such as macros.
A core row can be fragmented (contains gaps), since rows do not intersect objects such as power
domains. For this, the tool places end cap cells on both ends of the unfragmented segment.
Decap cells:
cells are temporary capacitors added in the design between power and ground rails to counter functional failures due to dynamic IR drop.Dynamic I.R. drop happens at the active edge of the clock at which a high percentage of Sequential and Digital elements switch.Due to this simultaneous switching a high current is drawn from the power grid for a small duration.If the power source is far away from a flop the chances are that this flop can go into a metastable state due to IR Drop.To overcome this decaps are added. At an active edge of clock when the current requirement is high , these decaps discharge and provide boost to the power grid. One caveat in usage of decaps is that these add to leakage current. De caps are placed as fillers. The closer they are to the flop’s sequential elements, the better it is.Decap cells are typically poly gate transistors where source and drain are connected to the ground rail, and the gate is connected to the power rail.
when there is an instantaneous switching activity the charge required moves from intrinsic and extrinsic local charge reservoirs as oppose to voltage sources. Extrinsic capacitances are decap cells placed in the design. Intrinsic capacitances are those present naturally in the circuit, such as the grid capacitance, the variable capacitance inside nearby logic, and the neighborhood loading capacitance exposed when the P or N channel are open.
One drawback of decap cells is that they are very leaky, so the more decap cells the more leakage. Another drawback, which many designers ignore, is the interaction of the decap cells with the package RLC network. Since the die is essentially a capacitor with very small R and L, and the package is a hug RL network, the more decap cells placed the more chance of tuning the circuit into its resonance frequency. That would be trouble, since both VDD and GND will be oscillating. I have seen designs fail because of this
Designers typically place decap cells near high activity clock buffers, but I recommend a decap optimization flow where tools study charge requirements at every moment in time and figure out how much decap to place at any node. This should be done while taking package models into account to ensure resonance frequency is not hit.
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