SVRF: Standard Verification Rule Format

SVDB: Standard Verification Dtabase (LVS results)

Completed layout is not necessarily “completely” complete. You may choose to verify a design when only part of it is complete. Calibre provides methods to verify partially completed layouts.

Input: 

Layout ( GDSII)

Logic (Verilog)

Rule file (SVRF ASCII text file

Output:

DRC result (drc.out)

Report (drc.rep.extrpt)

Log (drc.log)

Rule file:

♦ Provides run specifications (data file names, etc.)

♦ Defines layers  (Allow you to assign names to layers, making troubleshooting easier)

♦ Generates derived layers

♦ Defines design RuleChecks

♦ Defines devices

♦ Defines/extracts connectivity

♦ Drives Layout vs. Schematic comparisons

(using device recognition)

♦ Drives Parasitic Extraction (not covered in this class)

♦ Drives OPC/ORC (not covered in this class)

Rule file types:

Golden rule file (from factory)

Control rule file for site/run

User rule file for managing result

Calibre "merges" all rule files into a single file at run time

(the .rule file has many: INCLUDE xxxx.rule )

Typical DRC Rules