grep 'pattern' file #最基本的形式，显示匹配的行
grep -l 'pattern' * # 显示所有匹配pettern的文件名
grep -n 'pattern' file # 在匹配行之前加行号
grep -i 'pattern' file #显示匹配行，pattern不区分大小写
grep -v 'pattern' file # 显示所有不匹配行
grep -c 'pattern' file # 只显示匹配行数
2013年9月15日星期日
2013年9月11日星期三
DRC & ERC
DRC
Perform the design rule checking (DRC) process to evaluate the design for compliance with layout fabrication rules.
- Internal layer checks
- Wide metal checks
- Layer-to-layer checks
- All design checks are performed hierarchically
- Incremental DRC by layer or cell
ERC (Electrical Rule Checking)
Check for antenna violations and to make sure devices have a path through to a specific net
- Antenna checking with back annotation into Astro
- Through device path checking
Output:
DRC results show compliance with minimum/maximum/exact widths, spacings, enclosures, and other requirements. DRC runs can verify the correctness of the design mask set.
Procedure:
The Custom Designer platform DRC process operates on OpenAccess or Stream format data. You can optionally stream the DRC information to GDSII, and then run the DRC process on the .gds file.
Calibre:
You can use the Mentor Graphics Calibre and Calibre Interactive tools for design rule checking on the Custom Designer platform.
Calibre Interactive
The invocation GUI for Calibre DRC, LVS and xRC tools for physical verification and parasitic extraction.
Easily accessed from the menu bar within popular layout design environment(ICC).
提供用户方便快捷的进入方式，可以让designers在其熟悉的IC design environment里进行physical verification 或 extraction.
Calibre RVE tool:
results viewing environment
UNIX 技巧
在当前目录及子目录下根据文件名寻找文件
find . -name " *pattern* "
增加文件格式限制
find . -name " *pattern*" -type d #dir, f: regular file#
找到*pattern*的文件并删除
find . -name " *pattern* " -exec rm {} \; # 包括 ;
避开某个目录
find . -name " *pattern* "
增加文件格式限制
find . -name " *pattern*" -type d #dir, f: regular file#
找到*pattern*的文件并删除
find . -name " *pattern* " -exec rm {} \; # 包括 ;
避开某个目录
比如要在/usr/sam目录下查找不在dir1子目录之内的所有文件
find /usr/sam -path "/usr/sam/dir1" -prune -o -print
find / -amin -10 #查找在系统中最后10分钟访问的文件
find / -atime -2 #查找在系统中最后48小时访问的文件
find / -empty #查找在系统中为空的文件或者文件夹
find / -group cat #查找在系统中属于groupcat的文件
find / -mmin -5 #查找在系统中最后5分钟里修改过的文件
find / -mtime -1 #查找在系统中最后24小时里修改过的文件
find / -nouser #查找在系统中属于作废用户的文件
find / -user fred #查找在系统中属于FRED这个用户的文件
2013年9月10日星期二
VIM_技巧_左右对齐
对齐：左对齐，右对齐，居中对齐
将指定的lines靠左对齐
: {range} left {margion}
example:
: 1,15 left (全部贴边)
: 1, 20 left 4 (左边全部空开4格)
右：
: {range} right {margin}
中：
: {range} center
将指定的lines靠左对齐
: {range} left {margion}
example:
: 1,15 left (全部贴边)
: 1, 20 left 4 (左边全部空开4格)
右：
: {range} right {margin}
中：
: {range} center
每行的行首都添加一个字符串：%s/^/要插入的字符串
每行的行尾都添加一个字符串：%s/$/要插入的字符串
% 代表针对被编辑文件的每一行进行后续操作
$ 代表一行的结尾处
^ 代表一行的开头处
$ 代表一行的结尾处
^ 代表一行的开头处
2013年8月29日星期四
2013年8月28日星期三
Tap cell, Decap cell and end cap cells
endcap主要加在block level的 row end（2边） 和上下各一row ， 已经memory 或者其他block的周围包边，看TSMC 40ISF 的介绍，讲了PSE ( poly space effect）和OSE （od space effect）造成的影响，
主要意思是不能让poly和OD周围太空，不对称，密度太低，因此通过加endcap（通常是FILLER2 ，FILLER1没有OD ，不行）来满足均匀的密度， 是的std cell 周围的环境一致，
一般来说对block level是 必须做的，因为在chip level来看必须是一致的密度，
welltap这个就是偏置nwell和psub ， 适应7-track等小std cell， 一般为50~60um一个半径
来加，棋盘式加入， 这个不是40nm的独有， 早在180nm的时候就有了，
decap 就是去耦啊，特殊的filler cell， 可以降低动态电压降， 满足一定的电容值，
gate array类型的decap（比如tsmc的GDCAP）还可以起到eco cell的作用，
40nm就是多了个endcap， dfm更加重视些， 不能用FILLER1了
Placing the Well Tap Cells
These library cells connect the power and ground connections to the substrate and n-wells, respectively.
By placing well taps at regular intervals throughout the design, the n-well potential is held constant for proper electrical functioning.
The placer places the cells in accordance to the specified distances and automatically snaps
them to legal positions (which are the core sites).
Placing the End Cap Cells
These library cells do not have signal connectivity. They connect only to the power and ground rails once power rails are created in the design.
They also ensure that gaps do not occur between the well and implant layers.
This prevents DRC violations by satisfying well tie-off requirements for the core rows.
Each end of the core row, left and right, can have only one end cap cell specified. However, you
can specify a list of different end caps for inserting horizontal end cap lines, which terminate the
top and bottom boundaries of objects such as macros.
A core row can be fragmented (contains gaps), since rows do not intersect objects such as power
domains. For this, the tool places end cap cells on both ends of the unfragmented segment.
Decap cells:
cells are temporary capacitors added in the design between power and ground rails to counter functional failures due to dynamic IR drop.Dynamic I.R. drop happens at the active edge of the clock at which a high percentage of Sequential and Digital elements switch.Due to this simultaneous switching a high current is drawn from the power grid for a small duration.If the power source is far away from a flop the chances are that this flop can go into a metastable state due to IR Drop.To overcome this decaps are added. At an active edge of clock when the current requirement is high , these decaps discharge and provide boost to the power grid. One caveat in usage of decaps is that these add to leakage current. De caps are placed as fillers. The closer they are to the flop’s sequential elements, the better it is.Decap cells are typically poly gate transistors where source and drain are connected to the ground rail, and the gate is connected to the power rail.
when there is an instantaneous switching activity the charge required moves from intrinsic and extrinsic local charge reservoirs as oppose to voltage sources. Extrinsic capacitances are decap cells placed in the design. Intrinsic capacitances are those present naturally in the circuit, such as the grid capacitance, the variable capacitance inside nearby logic, and the neighborhood loading capacitance exposed when the P or N channel are open.
One drawback of decap cells is that they are very leaky, so the more decap cells the more leakage. Another drawback, which many designers ignore, is the interaction of the decap cells with the package RLC network. Since the die is essentially a capacitor with very small R and L, and the package is a hug RL network, the more decap cells placed the more chance of tuning the circuit into its resonance frequency. That would be trouble, since both VDD and GND will be oscillating. I have seen designs fail because of this
Designers typically place decap cells near high activity clock buffers, but I recommend a decap optimization flow where tools study charge requirements at every moment in time and figure out how much decap to place at any node. This should be done while taking package models into account to ensure resonance frequency is not hit.
主要意思是不能让poly和OD周围太空，不对称，密度太低，因此通过加endcap（通常是FILLER2 ，FILLER1没有OD ，不行）来满足均匀的密度， 是的std cell 周围的环境一致，
一般来说对block level是 必须做的，因为在chip level来看必须是一致的密度，
welltap这个就是偏置nwell和psub ， 适应7-track等小std cell， 一般为50~60um一个半径
来加，棋盘式加入， 这个不是40nm的独有， 早在180nm的时候就有了，
decap 就是去耦啊，特殊的filler cell， 可以降低动态电压降， 满足一定的电容值，
gate array类型的decap（比如tsmc的GDCAP）还可以起到eco cell的作用，
40nm就是多了个endcap， dfm更加重视些， 不能用FILLER1了
Placing the Well Tap Cells
Well taps are physical-only filler cells that are required by some technology libraries to limit
resistance between power or ground connections to wells of the substrate. Well-tap cells are
placed in a pre-placed status, so future placement commands do not move them.
The placer places the cells in accordance to the specified distances and automatically snaps
them to legal positions (which are the core sites).
Placing the End Cap Cells
These library cells do not have signal connectivity. They connect only to the power and ground rails once power rails are created in the design.
They also ensure that gaps do not occur between the well and implant layers.
This prevents DRC violations by satisfying well tie-off requirements for the core rows.
Each end of the core row, left and right, can have only one end cap cell specified. However, you
can specify a list of different end caps for inserting horizontal end cap lines, which terminate the
top and bottom boundaries of objects such as macros.
A core row can be fragmented (contains gaps), since rows do not intersect objects such as power
domains. For this, the tool places end cap cells on both ends of the unfragmented segment.
Decap cells:
cells are temporary capacitors added in the design between power and ground rails to counter functional failures due to dynamic IR drop.Dynamic I.R. drop happens at the active edge of the clock at which a high percentage of Sequential and Digital elements switch.Due to this simultaneous switching a high current is drawn from the power grid for a small duration.If the power source is far away from a flop the chances are that this flop can go into a metastable state due to IR Drop.To overcome this decaps are added. At an active edge of clock when the current requirement is high , these decaps discharge and provide boost to the power grid. One caveat in usage of decaps is that these add to leakage current. De caps are placed as fillers. The closer they are to the flop’s sequential elements, the better it is.Decap cells are typically poly gate transistors where source and drain are connected to the ground rail, and the gate is connected to the power rail.
when there is an instantaneous switching activity the charge required moves from intrinsic and extrinsic local charge reservoirs as oppose to voltage sources. Extrinsic capacitances are decap cells placed in the design. Intrinsic capacitances are those present naturally in the circuit, such as the grid capacitance, the variable capacitance inside nearby logic, and the neighborhood loading capacitance exposed when the P or N channel are open.
One drawback of decap cells is that they are very leaky, so the more decap cells the more leakage. Another drawback, which many designers ignore, is the interaction of the decap cells with the package RLC network. Since the die is essentially a capacitor with very small R and L, and the package is a hug RL network, the more decap cells placed the more chance of tuning the circuit into its resonance frequency. That would be trouble, since both VDD and GND will be oscillating. I have seen designs fail because of this
Designers typically place decap cells near high activity clock buffers, but I recommend a decap optimization flow where tools study charge requirements at every moment in time and figure out how much decap to place at any node. This should be done while taking package models into account to ensure resonance frequency is not hit.
Difference Between the route_zrt_eco and route_zrt_detail Commands
The
route_zrt_eco command performs ECO routing. It first connects the open nets and then fixes the DRC violations. The options control which nets are connected and on which areas of the chip the DRC violations are fixed.
The
route_zrt_detail command performs detail routing on a design. You run this command after running the route_zrt_track command. By default, the route_zrt_detail command analyzes the DRC violations in the entire design and then resolves those violations.
The key difference between the two commands is that you need to use the
route_zrt_eco command whenever you modify one or more nets. Officially, the route_zrt_eco command is used to perform incremental routing when you change the design, such as by inserting cells, upsizing cells, or downsizing cells. To fix DRC violations, you should use the route_zrt_detail -incremental command rather than the route_zrt_eco command.route_zrt_eco 通常是用在designer修改过电路之后，来perform incremental routing.
route_zrt_detail 通常用来修DRC violations;如 shorts, spacing, width, notch, gap, and end-of-line. 但如果是open net, 则要用
route_zrt_eco 来修
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