关于Clock Latency & Clock Uncertainty 略全面的解析（转自edaboard forum）

Let me try to clear up some of the confusing terminology - clear terminology allows for clear thinking.

The first important point is that there are two phases in the design of a clock signal. At first the clock is in "ideal mode" (e.g.: during RTL design, during synthesis and during placement). An "ideal" clock has no physical distribution tree, it just shows up magically on time at all the clock pins.
The second phase comes when clock tree synthesis (CTS) inserts an actual tree of buffers into the design that carries the clock signal from the clock source pin to the (thousands) of flip-flops that need to get it. CTS is done after placement and before routing. After CTS is finished, the clock is said to be in "propagated mode".

Now we can get to your questions:

What is clock latency? Clock latency is an ideal mode term. It refers to the delay that is specified to exist between the source of the clock signal and the flip-flop clock pin. This is a delay specified by the user - not a real, measured thing. (In fact there is 'clock source latency' and 'clock network latency' - the difference is not important for this discussion). When the clock is actually created, then that same delay is now referred to as the "insertion delay". Insertion delay (ID) is a real, measurable delay path through a tree of buffers. Sometimes the clock latency is interpreted as a desired target value for the insertion delay.

What is clock uncertainty? In ideal mode the clock signal can arrive at all clock pins simultaneously. But in fact, that perfection is not achievable. So, to anticipate the fact that the clock will arrive at different times at different clock pins, the "ideal mode" clock assumes a clock uncertainty. For example, a 1 ns clock with a 100 ps clock uncertainty means that the next clock tick will arrive in 1 ns plus or minus 50 ps.
A deeper question gets into *why* the clock does not always arrive exactly one clock period later. There are several possible reasons but I will list 3 major ones:
(a) The insertion delay to the launching flip-flop's clock pin is different than the insertion delay to the capturing flip-flop's clock pin (one paths through the clock tree can be longer than another path). This is called clock skew.
(b) The clock period is not constant. Some clock cycles are longer or shorter than others in a random fashion. This is called clock jitter.
(c) Even if the launching clock path and the capturing clock path are absolutely identical, their path delays can still be different because of on-chip variation. This is where the chip's delay properties vary across the die due to process variations or temperature variations or other reasons. This essentially increases the clock skew.

RC corner

• RC worst (also known as Delay corner) - Cc is min ,Cg x R is max

So we can say that there are overall 5 parasitic corners.

• Cbest
• Cworst
• RCbest
• RCworst
• Typical

Few definitions/information for every corner based on experience are…

C-best:

• It has minimum capacitance. So also known as Cmin corner.
• Interconnect is larger than the Typical corner.
• This corner results in smallest delay for paths with short nets and can be used for min-path-analysis.

C-worst:

• Refers to corners which results maximum Capacitance. So also known as Cmax corner.
• Interconnect resistance is smaller than at typical corner.
• This corners results in largest delay for paths with shorts nets and can be used for max-path-analysis.

RC-best:

• Refers to the corners which minimize interconnect RC product. So also known as RC-min corner.
• Typically corresponds to smaller etch which increases the trace width. This results in smallest resistance but corresponds to larger than typical capacitance.
• Corner has smallest path delay for paths with long interconnects and can be used for min-path-analysis.

RC-worst:

• Refers to the corners which maximize interconnect RC product. So also known as RC-max corner.
• Typically corresponds to larger etch which reduces the trace width. This results in largest resistance but corresponds to smaller than typical capacitance.
• Corner has largest path delay for paths with long interconnects and can be used for max-path-analysis.

Typical:

• This refers to nominal value of interconnect Resistance and Capacitance.

So you may have noticed that there are 2 types of parasitic- one is C-based and other is RC-based. In C-based C means worst and best case capacitance but in RC-based RC means  worst and best case R with adjustment in C towards worst or best but keeping the process planar. Based on the experience it was found that C-based extraction provides worst and best case over RC for internal timing paths because Capacitance dominates short wire. However for large design, inter-block timing paths were often worst with RC worst parasitic since R dominates for long wires.

Note: No corner guarantees min or max delay for an arbitrary transistor driving an arbitrary wire topology

With the help of below picture, you can easily understand what I am trying to tell you.

In the next blog, I will share more information about the parasitics corners from foundry point of view. In the sence, How metal thickness / Width / Space and all varies and how the foundry provides the data.

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