RC corner

• RC worst (also known as Delay corner) - Cc is min ,Cg x R is max

So we can say that there are overall 5 parasitic corners.

• Cbest
• Cworst
• RCbest
• RCworst
• Typical

Few definitions/information for every corner based on experience are…

C-best:

• It has minimum capacitance. So also known as Cmin corner.
• Interconnect is larger than the Typical corner.
• This corner results in smallest delay for paths with short nets and can be used for min-path-analysis.

C-worst:

• Refers to corners which results maximum Capacitance. So also known as Cmax corner.
• Interconnect resistance is smaller than at typical corner.
• This corners results in largest delay for paths with shorts nets and can be used for max-path-analysis.

RC-best:

• Refers to the corners which minimize interconnect RC product. So also known as RC-min corner.
• Typically corresponds to smaller etch which increases the trace width. This results in smallest resistance but corresponds to larger than typical capacitance.
• Corner has smallest path delay for paths with long interconnects and can be used for min-path-analysis.

RC-worst:

• Refers to the corners which maximize interconnect RC product. So also known as RC-max corner.
• Typically corresponds to larger etch which reduces the trace width. This results in largest resistance but corresponds to smaller than typical capacitance.
• Corner has largest path delay for paths with long interconnects and can be used for max-path-analysis.

Typical:

• This refers to nominal value of interconnect Resistance and Capacitance.

So you may have noticed that there are 2 types of parasitic- one is C-based and other is RC-based. In C-based C means worst and best case capacitance but in RC-based RC means  worst and best case R with adjustment in C towards worst or best but keeping the process planar. Based on the experience it was found that C-based extraction provides worst and best case over RC for internal timing paths because Capacitance dominates short wire. However for large design, inter-block timing paths were often worst with RC worst parasitic since R dominates for long wires.

Note: No corner guarantees min or max delay for an arbitrary transistor driving an arbitrary wire topology

With the help of below picture, you can easily understand what I am trying to tell you.

In the next blog, I will share more information about the parasitics corners from foundry point of view. In the sence, How metal thickness / Width / Space and all varies and how the foundry provides the data.