UNIX job 管理

暂停：
ctrl + z
%: bg    ## 重新开始，并且把foreground job放到了background

开启 background jobs：
在command后端加 &
比如：    du -sh * &

查看正在运行的background jobs：
%: jobs

把background jobs 推到 foreground：
%: fg

关掉background jobs：
%: kill %1     ## 数字是background job 的编号

VIM ---- Removing duplicate lines

STEP 1:

sort all lines 

:sort u

STEP 2:

remove duplicates , the first leaves only the last line, the second leaves only the first line.

g/^\(.*\)$\n\1$/d
g/\%(^\1$\n\)\@<=\(.*\)$/d

Breakdown of the second version:

g//d <-- Delete the lines matching the regexp
\@<= <-- If the bit following matches, make sure the bit preceding this symbol directly precedes the match
\(.*\)$ <-- Match the line into subst register 1
\%( ) <--- Group without placing in a subst register.
^\1$\n <--- Match subst register 1 followed by end of line and the new line between the 2 lines

vim大小写转换

vim中大小写转化的命令是
gu或者gU
形象一点的解释就是小u意味着转为小写；大U意味着转为大写.

剩下的就是对这两个命令的限定（限定操作的行，字母，单词）等等

1、整篇文章大写转化为小写
  打开文件后，无须进入命令行模式。键入:ggguG

解释一下：ggguG分作三段gg gu G
gg=光标到文件第一个字符
gu=把选定范围全部小写
G=到文件结束

2、整篇文章小写转化为大写
  打开文件后，无须进入命令行模式。键入:gggUG

解释一下：gggUG分作三段gg gU G
gg=光标到文件第一个字符
gU=把选定范围全部大写
G=到文件结束

3、只转化某个单词

guw 、gue
gUw、gUe
这样，光标后面的单词便会进行大小写转换
想转换5个单词的命令如下：
gu5w、gu5e
gU5w、gU5e

4、转换几行的大小写
将光标定位到想转换的行上，键入：1gU 从光标所在行 往下一行都进行小写到大写的转换
10gU，则进行11行小写到大写的转换
以此类推，就出现其他的大小写转换命令
gU0        ：从光标所在位置到行首，都变为大写
gU$        ：从光标所在位置到行尾，都变为大写
gUG        ：从光标所在位置到文章最后一个字符，都变为大写
gU1G      ：从光标所在位置到文章第一个字符，都变为大写

关于Clock Latency & Clock Uncertainty 略全面的解析（转自edaboard forum）

Let me try to clear up some of the confusing terminology - clear terminology allows for clear thinking.

The first important point is that there are two phases in the design of a clock signal. At first the clock is in "ideal mode" (e.g.: during RTL design, during synthesis and during placement). An "ideal" clock has no physical distribution tree, it just shows up magically on time at all the clock pins.
The second phase comes when clock tree synthesis (CTS) inserts an actual tree of buffers into the design that carries the clock signal from the clock source pin to the (thousands) of flip-flops that need to get it. CTS is done after placement and before routing. After CTS is finished, the clock is said to be in "propagated mode".

Now we can get to your questions:

What is clock latency? Clock latency is an ideal mode term. It refers to the delay that is specified to exist between the source of the clock signal and the flip-flop clock pin. This is a delay specified by the user - not a real, measured thing. (In fact there is 'clock source latency' and 'clock network latency' - the difference is not important for this discussion). When the clock is actually created, then that same delay is now referred to as the "insertion delay". Insertion delay (ID) is a real, measurable delay path through a tree of buffers. Sometimes the clock latency is interpreted as a desired target value for the insertion delay.

What is clock uncertainty? In ideal mode the clock signal can arrive at all clock pins simultaneously. But in fact, that perfection is not achievable. So, to anticipate the fact that the clock will arrive at different times at different clock pins, the "ideal mode" clock assumes a clock uncertainty. For example, a 1 ns clock with a 100 ps clock uncertainty means that the next clock tick will arrive in 1 ns plus or minus 50 ps.
A deeper question gets into *why* the clock does not always arrive exactly one clock period later. There are several possible reasons but I will list 3 major ones:
(a) The insertion delay to the launching flip-flop's clock pin is different than the insertion delay to the capturing flip-flop's clock pin (one paths through the clock tree can be longer than another path). This is called clock skew.
(b) The clock period is not constant. Some clock cycles are longer or shorter than others in a random fashion. This is called clock jitter.
(c) Even if the launching clock path and the capturing clock path are absolutely identical, their path delays can still be different because of on-chip variation. This is where the chip's delay properties vary across the die due to process variations or temperature variations or other reasons. This essentially increases the clock skew.